1. Field of the Invention
The present invention relates to data processing circuits and methods of operation of such circuits, and in particular to a data processing circuit, and method of operation, for performing arithmetic processing on data signals input to the circuit.
2. Description of the Prior Art
Generally, when developing data processing circuits, such as integrated circuits, there is a desire to keep the circuit as small as possible. The space that an integrated circuit occupies is at a premium. The smaller an integrated circuit is, the less expensive it will be to manufacture and the higher the manufacturing yield. For this reason, measures that reduce the size of an integrated circuit are strongly advantageous.
Often a data processing circuit will be designed to have a number of modes of operation, and when developing such a data processing circuit, it is sometimes necessary to provide circuit elements that are used solely for particular modes of operation of the data processing circuit. With regard to the different modes of operation, there may be a requirement for a high speed, but relatively low precision processing mode, and a lower speed, but relatively high precision processing mode. As an example, in a first mode of operation, an arithmetic processing function, such as an addition, subtraction, multiplication or division function, may need to be applied at high speed to data signals input to the circuit. However, in a second mode of operation, the requirement for high speed may be sacrificed in order to enable a higher precision arithmetic processing operation to be performed.
One way to implement a data processing circuit with two such modes of operation is to provide a number of arithmetic processing units used in the high speed, low precision mode of operation, and some further, larger arithmetic processing units used in the slower, higher precision mode of operation.
However, the provision of separate arithmetic processing units for each mode of operation does not assist in the general aim of trying to keep the processing circuit as small as possible, since, in any particular mode of operation, there will be arithmetic processing units which are not being used. Clearly, if the number of elements used in the data processing circuit could be reduced, this would enable the size of the chip to be reduced, thereby reducing the cost.
Another general aim when developing data processing circuits is to try and reduce the power consumption of those circuits. It is becoming more commonplace for integrated circuits to be used in products which operate from battery power, such as portable laptop computers, mobile phones, personal organisers, etc. In such situations, it is clearly desirable to reduce the power consumption of these processing devices as much as possible, in order to improve the battery life of the products, i.e. the amount of time the products can be used for before needing to replace or recharge the batteries. However, it is not just in the area of battery powered products where power consumption is a concern. The higher the power consumption, then the greater the heat generated by the integrated circuit. Hence, there is generally a desire to reduce power consumption wherever possible.
Generally, the more circuit elements provided on the data processing circuit, the greater the power consumption, and this is another reason why it is desirable to reduce the number of circuit elements wherever possible.
Hence, it is an object of the present invention to provide a data processing circuit for performing arithmetic processing on data signals, which has a plurality of modes of operation, and which requires less arithmetic processing units than the above described prior art data processing circuits.